Data buffer: due to the low rate of I/O devices and the rate of CPU and memory is very high, so you must set up a buffer in the controller. In the output, with the high-speed data from the buffer staged by the host, and then to the rate at which I/O devices have to transfer the data in the buffer to the I/O devices; When the input buffer is used for temporary data from I/O devices, after being received a batch of data, then the data in the buffer and transmitted to the host at a high speed.
Error control: device controller is in charge of by I/O device transmits the data error detection. If discover error has occurred in the transfer of, usually to setting the error detection code, and report to the CPU, so the CPU to transfer this to void the data, and to transmit at a time. This can ensure the correctness of the data input.
Data exchange: this refers to between the CPU and controller, data exchange between the controller and equipment. For the former, is through a data bus, the data to the controller by the CPU in parallel, or parallel to read data from the controller; Is equipment for the latter, the data input to the controller, or from the controller to the equipment. Therefore, in the controller must set the data register.
Status: identify and report the status of equipment controller should take down the state of the equipment for the CPU. For example, only send when the device is in the ready state, the CPU can start controller read data from the device. To this end, a status register shall be set up in the controller, with each one of them to reflect the device of a certain state. When the CPU reads the contents of the register, you can understand the status of the device.
Receive and identify command: CPU can send a number of different commands to the controller, the equipment controller should be able to receive and identify these commands. Therefore, in the controller should have corresponding control register, used to store the received command and parameters, and decoding for the received command. Disk controller can receive the CPU, for example, Read, Write, and the Format of the article 15 different commands, and some command with parameters; Accordingly, in the disk controller has multiple registers and command decoder, etc.
Address recognition: just like the memory of each unit has an address, each device in the system also has an address, and device controller must be able to identify it controlled by the address of each device. In addition, in order to make the CPU to (or from) to write (or read) register data, these registers should be has a unique address.